A Liquid Crystal Display (LCD) may be used to display information using an electric field to control the arrangement of molecules within the liquid crystal. In particular, Thin Film Transistors (TFTs) may be used as switches for the electric field and thereby control the display of information on the LCD. TFTs may be fabricated by forming a polycrystalline semiconductor layer from an amorphous semiconductor layer formed on a substrate. In particular, TFTs may be fabricated using seed selection through ion channeling (SSIC).
FIGS. 1-3 show a method of fabricating a polycrystalline semiconductor layer according to the prior art. Referring to FIG. 1, an insulating layer 15, such as an oxide layer, is formed on a substrate 10, to a predetermined thickness. A polycrystalline semiconductor layer 20a is formed on the insulating layer 15 at a predetermined temperature to a predetermined thickness. For polysilicon the predetermined temperature may be about 630.degree. C. and the predetermined thickness may be about 800 .ANG..
Referring to FIG. 2, ions may be implanted into the polycrystalline semiconductor layer 20a to form an amorphous semiconductor layer 20b (e.g., for polysilicon, Silicon ions (Si+) may be implanted). The ion implantation step may be performed at a predetermined energy and dosage level. For example, implantation of silicon ions into polysilicon may be performed at 50 KeV and at a dosage in a range between about 1.4.times.10.sup.15 to about 2.0.times.10.sup.15 ions/cm.sup.2. The ion implantation may break some of the crystals within the polycrystalline semiconductor layer 20a and cause the polycrystalline semiconductor layer to become amorphous, wherein some crystals may remain to act as seeds for re-crystallization.
Referring to FIG. 3, the amorphous semiconductor layer 20b may be annealed at a predetermined temperature for a predetermined time (e.g., amorphous silicon may be annealed at a temperature in a range of about 600.degree. C. for about 48 hours). The annealing step may cause the seeds in the amorphous semiconductor layer 20b and at the interface between the insulating layer 15 and the amorphous semiconductor layer 20b to re-crystallize into the polycrystalline semiconductor layer 20c. In the case of polysilicon, the grain size of the re-grown crystals may be about 0.5 .mu.m so that the electrons therein have a mobility of about 80 m.sup.2 /Vs. Accordingly, the crystals re-grown from those seeds may be relatively small since crystallization occurs within the amorphous semiconductor layer 20b and at the interface between the amorphous semiconductor layer 20b and the insulating layer 15 (i.e., crystal growth occurs in two directions within the amorphous semiconductor layer 20b).
The size, defect density, and surface roughness of the formed polycrystalline semiconductor layer 20c may influence the performance of the TFT. In particular, polycrystalline semiconductors with a relatively small grain size, high defect density, or a relatively rough surface may exhibit higher resistivity, decreased field effect capability, and contribute to charge carrier scattering.
The ion dosage may be increased to reduce the number of seeds in the amorphous semiconductor layer and thereby increase the grain size. However, when the ion dosage is increased, the annealing time for growing relatively large crystals may increase substantially. For example, FIG. 4 illustrates graphs of maximum grain size versus annealing time at various silicon ion dose levels. In particular, to produce a polysilicon layer having grains with average sizes greater than about 1.0 .mu.m using a Si+ion dosage in a range between about 1.5.times.10.sup.15 ion/cm.sup.2 and about 5.times.10.sup.15 cm.sup.2, may require an annealing time of about 50 hours.